1. Field of the Invention
The present invention relates generally to semiconductor devices, and more particularly, to a semiconductor device including a shunt interconnection.
2. Description of the Background Art
SRAMs (Static Random Access Memories) have been known as one kind of volatile semiconductor devices. In the SRAM, memory cells are provided at crossing portions of complementary data lines (bit lines) and word lines arranged in a matrix. FIG. 30 is an equivalent circuit diagram of a memory cell portion in a conventional SRAM. Referring to FIG. 30, the memory cell in the conventional SRAM is formed of two access transistors A1 and A2, two driver transistors D1 and D2, and two high resistance load elements R1 and R2.
The two high resistance load elements R1 and R2 and the two driver transistors D1 and D2 form a flip-flop circuit. In the flip-flop circuit, two cross-coupled storage nodes N1 and N2 are formed. The flipflop circuit has two stable states, High (N1) and Low (N2), and Low (N1) and High (N2). One of the two states continues to be held as long as a prescribed power supply voltage is supplied.
One of the source/drain regions of access transistor A1 is connected with a bit line BIT. The other one of the source/drain regions of access transistor A1 is connected with the storage node N1 of the flip-flop circuit. One of the source/drain regions of access transistor A2 is connected with a complementary bit line BIT. The other one of the source/drain regions of access transistor A2 is connected with the storage node N2 of the flip-flop circuit. The gate electrodes of access transistors A1 and A2 are connected to a word line WL. Word line WL controls the on/off states of access transistors A1 and A2.
The drain regions of driver transistors D1 and D2 are connected with the other ones of the source/drain regions of access transistors A1 and A2, respectively, and the source regions of driver transistors D1 and D2 are connected to a ground line. The gate electrode of driver transistor D1 is connected with the other one of the source/drain regions of access transistor A2, and the gate electrode of driver transistor D2 is connected with the other one of the source/drain regions of access transistor A1. One ends of high resistance load elements R1 and R2 are connected with the other ones of the source/drain regions of access transistors A1 and A2, respectively. The other ends of high resistance load elements R1 and R2 are connected with a power supply line.
During a data writing operation, access transistors A1 and A2 are turned on by selecting word line WL. A voltage is forcibly applied on bit line pair BIT and BIT depending upon a prescribed logical value, the flip-flop circuit is set to one of the above-described states. During a data reading operation, access transistors A1 and A2 are turned on. The potentials at storage nodes N1 and N2 are transmitted to the bit line pair.
In such an SRAM, there has been a need for operating the device at a higher speed and with a lower voltage in recent years. In order to increase the operation speed, a reduction in the electrical resistance of a word line is an inevitable requirement. In order to operate the device with a lower voltage, the potential of the ground line must be stabilized at the ground level, which requires a reduction in the electrical resistance of the ground line as well.
It has been conventionally practiced for this purpose to form a word line and a ground line of polysilicon or polycide, and to form a main interconnection or a shunt interconnection of a metal film on the word line or ground line with an interlayer insulating film interposed therebetween. There is provided a connection region for a main interconnection or shunt interconnection each for 8 bits or 16 bits of memory cells, and the word line and ground line are electrically connected with the main interconnection or shunt interconnection in the connection region.
FIG. 31 is a diagram showing a memory cell in a conventional SRAM including a word line and a main word line.
Referring to FIG. 31, memory array 101 in the conventional SRAM includes a plurality of word decoder portions 102a and 102b, and memory mat portions 103a and 103b. In memory mat portion 103a, word lines 106a, 106b, 106c, and 106d are formed to extend from word decoder portion 102a at prescribed intervals. Complementary bit lines 105a and 105b are formed orthogonal to word lines 106a, 106b, 106c and 106d. Memory cells 104a and 104b are formed at crossing points of a word line and bit lines. A single main word line 107 corresponding to four word lines 106a, 106b, 106c and 106d is formed to electrically connect these word lines at word decoder portion 102a. Main word line 107 is formed of a metal such as aluminum
Thus, the single main word line 107 is electrically connected with word lines 106a, 106b, 106c and 106d at word decoder portion 102a, an electrical signal to word lines 106a, 106b, 106c and 106d may be transmitted through main word line 107. Main word line 107 is formed of a metal having a low electrical resistance, and therefore the electrical signal transmitted to word lines 106a, 106b, 106c and 106d is passed through main word line 107, transmission delay to word lines 106a, 106b, 106c and 106d may be reduced.
FIG. 32 is a layout of a memory cell in another conventional SRAM including a shunt interconnection.
Referring to FIG. 32, the memory cell in the conventional SRAM includes access transistors 108a and 108b, and driver transistors 110a and S10b. A word line 106 is formed on a semiconductor substrate so as to serve as the gate electrodes of access transistors 108a and 108b. Complementary bit lines 105a and 105b are formed on word line 106 with a first interlayer insulating film interposed therebetween. A shunt interconnection 107 of a metal film is formed on complementary bit lines 105a and 105b with a second interlayer insulating film interposed therebetween. Word line 106 and shunt interconnection 107 are electrically connected in a contact hole 109 formed in a region different from the memory cell region.
Thus, in the conventional SRAM, in order to increase the operation speed, the main word line or shunt word line is formed and electrically connected with a word line in a region other than a memory cell region such as the word decoder portion.
When a shunt interconnection of a metal film is formed, and a ground line and the shunt interconnection are connected in the connection region for shunt in order to reduce the electrical resistance of the ground line, the connection region is also formed in a region other than the memory cell region as is the case with the word line.
There has been an increasing need for high density integration of SRAMs in addition to the above need for increasing the operation speed and reducing the operation voltage. However, as shown in FIGS. 31 and 32, the connection region for connecting the main word line or shunt interconnection 107 with word line 106 should be secured separately from the memory cell region, which gives rise to difficulty in increasing the integration density of the SRAMs. This similarly applies to the case of forming the shunt interconnection for the ground line.